From fb5a321dd7c2848128b04b306f3e1e59c87a3f70 Mon Sep 17 00:00:00 2001
From: Stijn Kuipers <stijnkuipers@gmail.com>
Date: Thu, 29 Jun 2023 16:26:07 +0200
Subject: Initial Filedump

Tadaaa!!
---
 sw/.vscode/buildData.json |  30 ++++++++++++++
 sw/.vscode/stm32l4x.cfg   | 103 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 133 insertions(+)
 create mode 100755 sw/.vscode/buildData.json
 create mode 100755 sw/.vscode/stm32l4x.cfg

(limited to 'sw/.vscode')

diff --git a/sw/.vscode/buildData.json b/sw/.vscode/buildData.json
new file mode 100755
index 0000000..f72c846
--- /dev/null
+++ b/sw/.vscode/buildData.json
@@ -0,0 +1,30 @@
+{
+    "ABOUT1": "This file holds combined user and CubeMX generated Makefile workspace dependecies.",
+    "ABOUT2": "User should not edit this fields, instead it should edit 'c_cpp_properties.json'",
+    "ABOUT3": "This file is regenerated on 'Update workspace' task.",
+    "VERSION": "",
+    "LAST_RUN": "",
+    "cSources": [],
+    "asmSources": [],
+    "ldSources": [],
+    "cIncludes": [],
+    "asmIncludes": [],
+    "ldIncludes": [],
+    "cDefines": [],
+    "asmDefines": [],
+    "cFlags": [],
+    "asmFlags": [],
+    "ldFlags": [],
+    "buildDir": "",
+    "targetExecutablePath": "",
+    "cubeMxProjectPath": "",
+    "openOcdConfig": [],
+    "stm32SvdPath": "",
+    "ABOUT4": "---- Paths below are fetched from user-specific 'toolsPaths.json'. ----",
+    "gccExePath": "",
+    "gccInludePath": "",
+    "buildToolsPath": "",
+    "pythonExec": "",
+    "openOcdPath": "",
+    "openOcdInterfacePath": ""
+}
\ No newline at end of file
diff --git a/sw/.vscode/stm32l4x.cfg b/sw/.vscode/stm32l4x.cfg
new file mode 100755
index 0000000..496b47a
--- /dev/null
+++ b/sw/.vscode/stm32l4x.cfg
@@ -0,0 +1,103 @@
+# script for stm32l4x family
+
+#
+# stm32l4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest current target has 64kB ram, use 32kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0351
+      # Section 44.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter_khz 500
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
+	# Use MSI 24 MHz clock, compliant even with VOS == 2.
+	# 3 WS compliant with VOS == 2 and 24 MHz.
+	mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
+	mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
+	# Boost JTAG frequency
+	adapter_khz 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter_khz 500
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
-- 
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